Loop Pipelining and Optimization for Run Time Reconfiguration

Lack of automatic mapping techniques is a signi cant hurdle in obtaining high performance for general purpose computing on recongurable hardware. In this paper, we develop techniques for mapping loop computations from applications onto high performance pipelined con gurations. Loop statements with generalized directed acyclic graph dependencies are mapped onto multiple pipeline segments. Each pipeline segment is executed for a xed number of iterations before the hardware is recon gured at runtime to execute the next segment. The recon guration cost is amortized over the multiple iterations of the execution of the loop statements. This alleviates the bottleneck of high recon guration overheads in current architectures. The paper describes heuristic techniques to construct pipeline con gurations which have reduced total execution time including the runtime recon guration overheads. The performance bene ts which can be achieved using our approach are illustrated by mapping example application loop onto Virtex series FPGA from Xilinx.